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Certification Course in ASIC RTL Design and Verification

 

We have designed this course for serious VLSI job seekers to fully prepare them to the expectations of the industry standard and we are committed to provide 100% placement assistance. Candidates must take a written test to be eligible for joining this course.

In this course you will learn both ASIC design and verification concepts. Verilog is covered as part of design and systemVerilog/UVM are covered as part of verification. The course highlights are periodical tests followed by extensive lab sessions and mock interviews.

Design:

This course provides the solid foundations on ASIC design concepts. The course starts from the fundamentals , covers block level design from scratch, RTL coding , FSM coding techniques,  Verilog design & verification constructs,  Synthesis,  area and timing constraints,  finding critical paths in the design and optimization, Clock domain Crossing and metastability,  Low Power design techniques, memories, Xilinx FPGA design etc.    Exercises and interview preparation as part of this course are added advantage.

Verification:

Verification has become primary concern as all the companies want their IP to be fully verified before it goes to silicon. As a result, companies are spending more money on verification and the demand for verification engineers in the industry is growing day by day.

This course is designed to fully prepare the student to meet the verification challenges involved with medium size to complex IP’s.  SystemVerilog emerged as the industry’s key verification languages as it supports coverage driven verification coupled with CRT(Constrained Random Techniques). In this course, you will learn verification concepts such as functional coverage, verification plan, layered testbenches etc., and as part of systemVerilog,  OOPS concepts such as inheritance, polymorphism, encapsulation, and Constrained random techniques , coverage driven verification, virtual interfaces and call backs etc.

UVM(Universal verification methodology) is gaining universal acceptance as the de-facto verification methodology. UVM enables efficient development and reuse of verification environments. As part of this course, you will learn all UVM concepts such as UVM factory,UVC(UVM verification components), UVM sequencers, configuration database, sequence libraries,  TLM, virtual sequencer, register abstraction, callbacks etc.

 

Next batch starts on 30th March, 2019. 

Register here : https://www.sumedhait.com/register/

Course duration : 4.5 months

Fees : Rs 90,000 (including taxes)

 

Course Curriculum:

Main Topic Contents
ASIC and SOC What is ASIC & SOCs & FPGAs
SOC Design Flow Study different stages of ASIC design flow
Number Systems Analog Vs Digital
Binary numbers
Fixed and Floating point
Binary Octal Hexa Decimal
Binary Addition
Representation of Negative numbers
Sign-magnitude
1’s Complement & 2’s Complement
2’s Complement addition and Subtraction
Binary multiplication
Binary Codes, Gray Code, Excess-3 code, 2421 code, BCD code
Error Detecting and Correcting Codes Parity
Hamming codes
CRC codes
Checksum
Logic Simplification Boolean Algebra
Axioms
Principle of duality
Shannon’s theorem
Min terms and Max terms
Canonical SOP and POS
Algebraic Simplification
Simplification using k-map
Prime Implicants, Essential Prime Implicants, Finding minimal expression
Quine-McCluskey Method
Combinational Logic Part I SOC Design Flow
What is ASIC & SOCs & FPGAs
Study different stages of ASIC design flow
Gates, Fan-in, Fan-out, Noise Margin, Propagation Delay
Active High and Active Low logic
Levels of logic and propagation delay
Multiple outputs – Simplification
AND-OR, NAND-NAND, OR-AND, NOR-NOR
AND-OR-INVERT, OR-AND-INVERT
Universal gates, Inverting gates vs Non-inverting gates
Inhibition and Implication, Timing Hazards Static or Dynamic
Combinational Logic Part II Decoders, Encoders and Priority Encoders
Tri-State Buffers
Multiplexers
Comparators
Parity circuits
Iterative Circuits
Adders
Half adder
Full adder
Binary Adder
Adder Cum Subtractor
BCD adder
Fast Adders
Carry look ahead adder
Carry Skip adder
Carry Save adder
Carry Select Adder
Combinational Logic – Design examples. Some Indiustrial oriented designs using combi logic
Sequential Logic – Part 1 Combinational Vs Sequential Circuits
Latches, S-R Latch, J-K Latch
Flip-Flop, S-R Flip-flop, J-K Flip-Flop
Latch vs Flip-Flop
Race around Condition
Master Slave flip flop
Edge Triggered flip-flops
D-flop, T-Flop
Preset and Clear pins
Excitation tables and Characteristic equation
Sequential Logic – Part 2 Shift Registers
Universal Shift Register
Counters
Ripple Counters
Synchronous Counters
Divide-by-n counters
up/down counters
Design using State machines Mealay and Moore state machines
State table, State diagram, State reduction, State assignment Analysis,
Design, Mealy Vs Moore
Sequential Logic – Design examples. Some Industrial oriented designs using Seq logic
Design Rules/Logic Setup and hold timings
Maximum frequency of operation
Crtical Path
Clock Skew and Clock Jitter
Fixing set-up and Hold violations
Control and datapath design
Factoring State machines.
Design Examples – Part I
Design Examples – Part II
Metastability and Clock Domain Crossing Techniques
Reset Synchronization
Low Power Design – Clock Gating Techniques
Memories – ROM, SRAM, DRAM, SDRAM
Programmable logic Devices –
PLA, PAL, FPGA, CPLD
FPGA architecures Xilinx FPGAs
XC4000
Spartan
Virtex
Synthesizing and Implementing Designs
Verilog HDL Introduction to HDLs and RTL design
Data types
Verilog Constructs
Continuous assignments
Procedural assignment statements – blocking and non-blocking
Logical operators
Arithmetic Operators
Unsigned arithmetic
Signed arithmetic
Relational Operators
Equality Operators
Shift Operators
Vector Operations
Part Selects
Bit Selects
Conditional Expressions
Always Statement
If statement
Case Statement (CaseZ&CaseX Statements)
Inferring Latches from Case Statements
Full case, Parallel case
Module Instantiation Statement
Parametered Designs
Structural, Behavioral, Dataflow modelling in verilog
Modelling in Verilog Combinational logic using verilog
Sequential logic using verilog
Coding FSMs in Verilog
Coding Mealy FSMs in Verilog
Coding Moore FSMs in Verilog
Design Examples using verilog
Optimizations in Verilog Resource allocation
common Subexpressions
Moving Code
Common factoring
Avoiding latches
Reusable and modular design using Verilog Parameterized design
Verilog Function
Verilog Generate Construct
Verilog `ifdef
Verification using verilog Verilog testbench
Non-synthesizable constructs in verilog
Initial statement
for loop,repeat
while loop
force, release
fork and join
Functions and Tasks in verilog $finish,$stop
$display,$monitor
$time,$realtime
$random
$readmemb,$writememb
$fopen,$fclose
Design Techniques Memory modeling using verilog
RTL Coding Guidelines – Dos and Donts
Synthesis Overview
Simulation and Synthesis mismatches
Constraining Designs
DFT Introduction
DFT basics
Faulty models,detection,simulation
Test Pattern generation
Scan based BIST
Scan Cells Designs
Scan Architectures
Scan Design Flow
Verification Guidelines
Introduction
The Verification Process
The Verification Plan
The Verification Methodology Manuals
Basic Testbench Functionality
Directed Testing
Methodology Basics
Constrained Random Stimulus
What should you Randomize
Functional Coverage
Testbench Components
Layered Testbench
Building a Layered Testbench
Simulation Environment Phases
Maximum Code Reuse
Testbench Performance
HVL System Verilog
Datatypes Introduction
Built-in Data Types
Fixed Size Arrays
Dynamic Arrays
Queue
Associative Arrays
Linked Lists
Array Methods
Choosing a Storage Type
Creating New Types with typedef
Creating user-defined structure
Enumerated types
Constant
Strings
Expression width
Net types
Procedural Statements And Routines Introduction
Procedural Statements
Tasks,Functions, and Void Functions
Task and Function Overview
Routine Arguments
Returning from a Routine
Local Data Storage
Time Values
Basic OOP Introduction
Think of Nouns,not verbs
First Class
Defining a Class
OOP Terminology
Creating New Objects
Object Deallocation
Using Objects
Static Variables vs Global variables
Class Routines
Defining Routines outside
of the Class
Scoping Rules
Using one class inside another
Understanding dynamic objects
copying objects
Public vs Private
Straying Off a course
Building a Testbench
Connecting The Testbench And Design Introduction
Separating the Testbench and Design
The Interface Construct
Stimulus Timing
Interface Driving and Sampling
Connecting It All Together
Top Level Scope
Program – Module interactions
SystemVerilog Assertions
The Four-Port ATM Router
Randomization Introduction
What to Randomize
Randomization in SystemVerilog
Constraint Details
Solution Probabilities
Controlling Multiple Constraint Blocks
Valid Constraints
In-line Constraints
The pre_randomize and post_randomize Functions
Constraint Tips and Techniques
Common Randomization Problems
Iterative and Array Constraints
Atomic Stimulus generation vs scenario generation
Random Control
Random Generators
Random Device Configuration
Threads and Interprocess Communication Introduction
working with thread
Inter process Communication
Events
Semaphores
Mailboxes
Building a Testbench with Threads and IP
Advanced OOP and Guidelines Introduction
Introduction to Inheritance
Factory Patterns
Type Casting and
Virtual methods
Composition,Inheritance and Alternatives
Copying an Object
Callback
Functional Coverage Introduction
Coverage Types
Functional Coverage Stratagies
Simple Functional Coverage Example
Anatomy of a cover group
Triggering of a cover
group
Data Sampling
Cross Coverage
Coverage Options
Parameterized Cover Groups
Analyzing Coverage Data
Measuring Coverage Statistics during simulation
Universal Verification Methodology (UVM)
Introduction
A Conventional Testbench for the TinyALU
SystemVerilog Interfaces and Bus Functional Models
Object Oriented Programming(OOP)
Classes And Extension
Polymorphism
Static Methods and Variables
Parameterized Class Definitions
The Factory Pattern
An Object Oriented Testbench
UVM Tests
UVM Components
UVM Environments
A New Paradigm
Talking to Multiple Objects
Using Analysis Ports in a Testbench
Interthread Communication
Put and Get ports in Action
UVM Reporting
Class Hierarchies and Deep Operations
UVM Transactions
UVM Agents
UVM sequences
Onward with the UVM
SOC Design and Industrial Practices
Clocking Synhchronous Clocking
Source Synchronous Cloking
Embedded Clocking
FIFO design Synchronous FIFO design
Asynchronous FIFO design and gray pointers
FIFO depth Considerations
Reset Schemes Asynchronous reset scheme
Reset Synchronizer
Synchronous reset scheme
Flop based or SRAM based
Throughput Methods to increase throughput
Higher Frequency
Wider Data-path
Pipelining
Throughput
Parallel Processing
Out-of-order execution
Caching
Pre-fetching
Multi-cores
Latency Methods to reduce latency
Flow Control Introduction
Valid and ack
Credit based flow control
Pipeline Operation Introduction to Pipeling
A Simple Example
RISC,a pipelined processor
Piplelined vs parallel Operation
Piplelined Adder
Parallel Adder
ClockingArbitration Introduction to Arbitration
Common Arbitration Schemes
Strict priority Arbitration
Round Robin Arbitration
Weighted Round Robin
Industry Standard Bus Interfaces AMBA Bus
APB/AHB
AHB Lite Controller Design
Serial interfaces – UART as example
MIPS Processor Introduction
Instruction Set
Architecture
Implementation
Advanced Low Power Design Techniques Power Gating
Voltage and Frequency Scaling