Your search for the best VLSI training institute ends here


Join Sumedha to Master Definition to Design and Synthesis to signoff.

SumedhaIT is the best VLSI institute in India with a core objective to provide 100% job oriented course in “VLSI Physical Design”.  The course is designed and managed by IIT / IISc alumni and is designed as required by the industry following latest low power, nano scale and complex designs. The course is taught by industry professionals to ensure the latest design methodologies are followed with industry and standard EDA tools. Very-large-scale integration (VLSI) is the process of creating an integrated circuit for a chosen functionality using millions of transistors and integrating them into a single chip.

SumedhaIT is managed by professionals with over 20+ years of rich VLSI design experience. The course is designed to ensure the students understands and implements RTL to GDS , in that process we ensure that each student  appreciates each and every class. Success of the student depends on his / her ability to understand simple concepts and apply the same on complex situations. We give equal importance to both basics and advanced topics and ensure the student gets a true experience of what chip design is.

More than 70% of the course delivery happens in doing practical design’s. The student is expected to dedicate all his time for 6 months. SumedhaIT transforms the graduates into a full-fledged VLSI Physical Design Engineer.

End of the course the student has to attend a 3rd party certification exam and he / she will be awarded a certificate by Govt of India &  Electronics Sector Skill Council .

Course Objectives

Getting hands on experience in basic to complex digital chip design flow starting from RTL netlist to GDSII. The flow also includes analyzing reports / constraints and tweaking the same to meet Power , performance and Area goals at various stages.

Course Syllabus

VLSI Physical Design involves thorough understanding of basic digital design, CMOS fundamentals, Partitioning , Floor planning , Place & route , Static Timing Analysis (STA ), timing closure, Signal Integrity analysis, parasitic (RC) extraction, Power analysis, Physical verification, Electrical verification, DFM/DFY and Tapeout related topics.

The course starts with pre-requisite courses in Unix OS, Programming & Shell/Perl / TCL scripting languages. To appreciate the concepts better student should be prepared to attempt all assignments, Labs. This will ensure the students pass with flying colors.


  1. Introduction to VLSI Design

  2. Basic Electronics and CMOS fundamentals

  3. Basic Digitals ( Combinational & Sequential ) Design concepts

  4. Inverter , STD Cell Design concepts

  5. Hardware Description Language Techniques

  6. Introduction to Static Timing Analysis

  7. Mini Project

  8. Synthesis  – SDC ( Synopsys Design Constraints )

  9. Timing Constraints & STA (Detailed)

  10. Design Patitioning

  11. Design Floor Planning and Power Planning

  12. Design Placement

  13. Clock Tree Synthesis

  14. Design Routing

  15. Parasitic Extration and Timing Analysis

  16. Signal Integrity

  17. IR Drop Analysis

  18. OCV Analysis

  19. Low Power Design Techniques

  20. Physical Verification

  21. Electrical Verification

  22. SignOff

  23. Major Project


All fresh and experienced professionals with electronics degree B.Tech / M.Tech or MSc electronics having 65% or above.

 Course Format

 The class will consist of class room lecture, of duration 2.5 hrs daily and  6 hrs of lab. Lab access is unlimited.

Course duration: 5 months

Course Fees: Rs. 99,000 (including taxes)

Next batch starts on 30th March, 2019

Register here for admission : https://www.sumedhait.com/register/