CERTIFICATE COURSE IN VLSI PHYSICAL DESIGN
Your search for the best VLSI training institute ends here
Join Sumedha to Master Definition to Design and Synthesis to signoff.
SumedhaIT is the best VLSI institute in India with a core objective to provide 100% job oriented course in “VLSI Physical Design”. The course is designed and managed by IIT / IISc alumni and is designed as required by the industry following latest low power, nano scale and complex designs. The course is taught by industry professionals to ensure the latest design methodologies are followed with industry and standard EDA tools. Very-large-scale integration (VLSI) is the process of creating an integrated circuit for a chosen functionality using millions of transistors and integrating them into a single chip.
SumedhaIT is managed by professionals with over 20+ years of rich VLSI design experience. The course is designed to ensure the students understands and implements RTL to GDS , in that process we ensure that each student appreciates each and every class. Success of the student depends on his / her ability to understand simple concepts and apply the same on complex situations. We give equal importance to both basics and advanced topics and ensure the student gets a true experience of what chip design is.
More than 70% of the course delivery happens in doing practical design’s. The student is expected to dedicate all his time for 6 months. SumedhaIT transforms the graduates into a full-fledged VLSI Physical Design Engineer.
End of the course the student has to attend a 3rd party certification exam and he / she will be awarded a certificate by Govt of India & Electronics Sector Skill Council .
Getting hands on experience in basic to complex digital chip design flow starting from RTL netlist to GDSII. The flow also includes analyzing reports / constraints and tweaking the same to meet Power , performance and Area goals at various stages.
VLSI Physical Design involves thorough understanding of basic digital design, CMOS fundamentals, Partitioning , Floor planning , Place & route , Static Timing Analysis (STA ), timing closure, Signal Integrity analysis, parasitic (RC) extraction, Power analysis, Physical verification, Electrical verification, DFM/DFY and Tapeout related topics.
The course starts with pre-requisite courses in Unix OS, Programming & Shell/Perl / TCL scripting languages. To appreciate the concepts better student should be prepared to attempt all assignments, Labs. This will ensure the students pass with flying colors.
Introduction to VLSI Design
Basic Electronics and CMOS fundamentals
Basic Digitals ( Combinational & Sequential ) Design concepts
Inverter , STD Cell Design concepts
Hardware Description Language Techniques
Introduction to Static Timing Analysis
Synthesis – SDC ( Synopsys Design Constraints )
Timing Constraints & STA (Detailed)
Design Floor Planning and Power Planning
Clock Tree Synthesis
Parasitic Extration and Timing Analysis
IR Drop Analysis
Low Power Design Techniques
All fresh and experienced professionals with electronics degree B.Tech / M.Tech or MSc electronics having 65% or above.
The class will consist of class room lecture, of duration 2.5 hrs daily and 6 hrs of lab. Lab access is unlimited.
Course duration: 6 months
Course Fees: Rs. 80,000 + GST
Next batch starts from 3rd December, 2018